1. Technical Field
This disclosure relates in general to bias-regulated crystal oscillators (briefly X-Osc) and in particular to a way of reliably detecting a state of regulation of the bias current of the oscillator for regulating a timeout period at start-up.
2. Discussion of Prior Art
It is customary to regulate the amplitude of the signal generated by an X-Osc by acting on the X-Osc driver circuit current to keep substantially constant the output signal amplitude and equal to a reference value.
Amplitude regulation eliminates any effect of nonlinear behavior of the driver circuit, therefore the oscillation waveform is cleaner and the crystal itself is safely driven. Without any regulation mechanism both spectral purity and current consumption would be negatively affected.
FIG. 1 shows a basic circuit diagram of a Pierce Crystal Oscillator's driver circuit (the most commonly used architecture) with current regulation. The bock BIAS REGULATOR senses the oscillation and modifies the BIAS CONTROL VOLTAGE until the large signal driver parameters (e.g. large-signal gm) meet the critical values that determine a stable oscillation. Equilibrium is reached when the driver negative output resistance balances the total load resistance, the actual value of which, because of the high Quality Factor of the crystal, is close to the crystal motional resistance).
FIG. 2 shows a typical oscillating voltage and regulating current of the basic circuit of FIG. 1.
Whenever start-up time is an issue, as is the case in stand-alone digital systems, the start-up current of the driver circuit bias current generator should be configurable in order to get the most from the crystal in quickly reaching a stable operation.
On another account, it is important that the master X-Osc of a digital system generate a waveform of adequate quality before a reset process may correctly be initiated and attainment of this indispensable condition is normally assumed to have been reached in a grossly empirical manner by digitally implementing a timeout long enough to reasonably assume that the sinusoidal oscillation generated by the X-Osc has stabilized itself in terms of spectrum and amplitude.
Normally, this timeout digital delay is implemented by counting a given number of clock pulses either with a dedicated counter or alternatively by firmware if a microprocessor or microcontroller is contemplated in the application.
FIG. 3 shows the circuit diagram of FIG. 1, including a BUFFER and a DIGITAL DELAY block for implementing a proper timeout at system start up.
The BUFFER circuit produces a clean square wave from the oscillator's sinusoidal wave.
After the oscillator is enabled, a finite amount of time elapses before the oscillation builds up and the Buffer outputs a first pulse (re: FIGS. 4, 5). Moreover, because the quality of the first CK pulse is rather poor (re: FIG. 4), additional idling time is necessary prior to enabling the CLOCK DISTRIBUTION circuit.
According to the art, a clock pulse count DIGITAL DELAY is employed for introducing a timeout long enough to ensure that the oscillation (having regulation of the X-Osc acting from the stat-up instant) has surely stabilized, under any worst case circumstances. The timeout delay is imposed either by the use of dedicated clock pulse counter or by firmware if a microprocessor or microcontroller is contemplated in the application.
This approach is clearly unrelated to the physical-electrical parameters of the crystal oscillator circuit that may affect its start-up behavior and does not specifically take into account differences among the wealth of crystals and packaging coming from different vendors, which may introduce further uncertainty of both time constant and start-up timing.
In general purpose applications, a timeout delay time is established from worst case analysis overestimation and may in fact be unreasonably longer than necessary by excess precaution.
Where the start-up timing is an issue (e.g. in low power application with short periods of activity or whenever an excessive idle time means waste of energy) the approach of the prior art is unsatisfactory.
Moreover, configurability of the bias current to quicken the start-up process adds an additional level of complexity to the problem because any change in the configured start-up bias conditions may strongly affect the time constant of the X-Osc leading to a precautionary increase of the digitally defined timeout delay and thus of the overall start-up time.